Among the most important requirements in an avionics system is to ensure the time and space partitioning of the running processes. Time partitioning is a technique which guarantees that the threads within a process get a predetermined portion of the processor time. To ensure that a predetermined portion of the processor time is sufficient to complete the thread execution, usually a safety margin is added on top of the measured Worst-Case Execution Time (WCET). Space partitioning refers to hardware-enforced limitations on memory accesses which prevent processes from corrupting each other's data. The time and space partitioning is guaranteed by a Real-Time Operating System (RTOS), typically running on a Commercial-Off-The-Shelf (COTS) single-core processor.
The complexity and computing power of avionics systems are ever increasing, while COTS single-core processors are becoming obsolete. Therefore, it is necessary to select new computer architectures to satisfy the avionics system needs. The available COTS multi-core processors tend to be some of the best candidates because of the high performance capabilities along with low Size, Weight and Power (SWaP) profile. Apart from the benefits, the COTS multi-core processors suffer from temporal effects of unpredictable contentions. As a result of the unpredictable contentions, the time-partitioning might be jeopardized.
Unpredictable contentions are introduced by accesses from multiple cores to the same shared hardware resources. Examples of shared hardware resources are caches, main memory, and Input/Output (I/O) interfaces. Unpredictable contentions result in conservative task timings and consequent penalized processor performance. Thus, there is a need to have a performance efficient technique which tackles the temporal effects of shared hardware resources in COTS multi-core processors.
In a COTS multi-core processor, the cache is a hardware resource, in which availability highly impacts application performance. If the cache is shared among the processor cores, then tasks mapped on different cores might invalidate each other's cache lines. As a result of the cross-core cache invalidation, the processor performance might be penalized.
In order to reduce the cross-core cache invalidation and respectively increase the processor performance, various approaches have been developed. In one approach, cache partitioning is provided via a mechanism called “memory pools” in the Deos RTOS from DDC-I that allows fine-grain control over which memory pages are included in each memory pool.
Although the memory pool concept has been successfully applied to partition the cache, there is still a high unpredictable contention in a COTS multi-core processor caused by significant interference in the main memory, which can be a Dynamic Random Access Memory (DRAM). The main memory is accessed by the processor with the help of one or multiple memory controllers.
In another approach, DRAM bank and cache coloring has been implemented using Linux kernel extensions to control the Memory Management Unit (MMU). This approach suggests that partitioning of the cache and main memory can bring a substantial performance improvement.
Accordingly, there is a need for addressing the problem of providing a performance-efficient partitioning of the memory hierarchy in a COTS multi-core processor.